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STA 课程大纲 1. Introduction of Static Timing analysis Basic Concept: timing path, setup check , hold check ; position of implementation flow; timing analysis flow 2. Constraint Clock; input delay; output delay; port cap; wire load models ; design rules constraints; ideal networks 3. Generating timing report Interpreting Timing Arcs; Generating setup and hold reports, Timing paths of interest; Report Four additional checks ; Generating Summary reports 4. Operating Conditions Analysis mode ; minimum and maximum delay calculations; Derating Factors; CRPR; wire load model, Library, 5. Delay calculation Nonlinear delay models; CCS model ; waveform Propogation; 6. Back Annotation Star-RC; SDF file; detailed parasitics 7. timing path(path group) and Exceptions Path groups ; path timing reports ; path timing calculation; Timing exception: multicycle path ; max delay; min delay 8. Variation OCV; AOCV 9. Constraints checking Constraints In a timing report; constraint issues; constraint multiple clocks; debuging 10.Analysisi Flow Timing analysis flow; analyzing four specific situations; path-based analysis; best proctises 11.Signal integrity Crosstalk delay; inputs ; crosstalk noise; improving accuracy; 12.ECO flow ECO loop; fixing timing violations; replaying; ECO change list 13.useful skew concept and How to handle using ICC? 14.Hierarchical models QTM; ILM; ETM; model validation; Hierarchical Scope checking; 15. Summary

 
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